1. Field of the Invention:
This invention relates to a method of forming a local interconnect and a semiconductor device comprising a local interconnect. The semiconductor device comprises:                a) a dielectric oxide layer; and        b) a conductivity structure comprising:        i) at least one barrier layer having a thickness of 10-200 Å on a surface of said oxide layer; and        ii) a conductive layer comprising titanium, on said at least one barrier layer, said at least one barrier layer preventing diffusion of oxygen from said dielectric oxide layer into said conductive layer and having a corresponding oxide that is not soluble in said conductive layer.        
2. Discussion of the Background:
Integrated circuits comprise individual devices which are electronically connected through a series of metallization layers and vias. Vias are conductive connections formed through dielectric layers which provide an electrical connection to an active region of a semiconductor device. Vias to individual devices which are located within close proximity to each other, may be connected by a series of local interconnects. A local interconnect is a patterned metal layer, formed parallel to the plane of the semiconductor substrate, which locally connects vias. A series of vias and local interconnects may also connect an active region of a semiconductor device to a global interconnect layer, wherein the active region and global interconnect layer are separated by multiple dielectric layers.
The electrical conductivity of these local interconnects should be high, insofar as increased resistivity will reduce the speed and performance of the device.
Ti local interconnects are generally formed of a thin metal layer, typically of from 500 ∈ to 3 k∈. After patterning a Ti line, a layer of dielectric film will be deposited followed by a planarization process. During later processes which subject a Ti line to elevated temperatures, Ti will absorb oxygen from an oxygen containing dielectric material. This results in a Ti film of increased resistivity due to dissolution of oxygen in the Ti. In order to compensate for increased film resistance, Ti thicknesses have been increased. Increased Ti thicknesses result in more expensive processing because of 1) difficulties in dielectric filling of high aspect ratio Ti line gaps; and 2) increased planarization time, such as CMP, needed to plannarize a thick dielectric layer to achieve global planarization.
Accordingly, an interconnect having good conductivity, and an efficient method for forming the same is desired.